A conventional ECL/CML to TTL translator circuit 10, coupled between an ECL/CML gate 12 and a TTL gate 14 is illustrated in FIG. 1. The ECL gate 12 provides the input to the translator section 10 and the ECL gate voltage levels are referenced to the higher reference voltage level positive power rail V.sub.CC (ECL). The translator section 10 in turn provides the input to drive the TTL gate 14. The TTL gate voltage levels are referenced to the lower reference voltage level ground power rail GND (TTL). The ECL gate 12 includes ECL input transistors Q1 and Q2 with emitter nodes tied together to the ECL tail current source transistor element Q3 and tail resistor R3. Current source transistor element Q3 is provided with base drive current by tail current source voltage V.sub.CC and sources tail current through tail resistor R3 to a low voltage level V.sub.EE which in this example may be ground potential GND. The ECL input transistors Q1 and Q2 provide alternative collector lead resistor current paths through swing resistors R1 and R2. Complementary high and low logic base current levels at the complementary inputs I.sub.TN (1) and I.sub.TN (0) at the respective base nodes of the input transistors Q1 and Q2 determine which transistor is conducting for conducting tail current generated by current source transistor element Q3 through the respective swing resistor.
The complementary outputs of ECL gate 12 are taken from the respective collector nodes of ECL input transistors Q1 and Q2. The voltage swing between the logic high and low level output signals is established by the magnitude of the tail current generated by current source transistor element Q3 and tail resistor R3, and by the swing resistors R1 and R2 which are generally of equal value. The complementary output signals are delivered through emitter follower output buffer transistor elements Q1A and Q2A respectively.
In the conventional translator circuit 10 of FIG. 1, the emitter follower output transistor elements Q1A and Q2A are coupled in respective branch circuits 15,16 of a current mirror circuit. The current mirror circuit is established by current mirror transistor elements Q4 and Q5 coupled in current mirror configuration with respective collector lead resistors R4 and R5. Transistor element Q4 is a base collector shorted (BCS) transistor. Resistors R4 and R5 are of equal value and resistor R4 establishes the current level in the branch circuit 15 which is mirrored in branch circuit 16.
The current flowing in branch circuit 15 is established by resistor R4 and the voltage drop across resistor R4 which is dependent upon V.sub.CC. Analysis reveals that resistor R5 in branch circuit 16 shifts the reference voltage level of the output signal on line 16 from V.sub.CC to ground potential at the collector node of the second current mirror transistor Q5. This is because the V.sub.CC dependency of the voltage drop across resistor R5 is cancelled by the V.sub.CC dependency of the current mirrored in branch circuit 16 from branch circuit 15. With the V.sub.CC dependencies offsetting and cancelling each other in branch circuit 16, the voltage level at the collector node of current mirror transistor Q5 is set with reference to the TTL ground potential level GND (TTL).
The reference voltage level shifted output signal from the collector node of current mirror transistor Q5 is coupled directly to the base node of inverting stage transistor Q6 which in turn controls the phase splitter transistor element Q9 of the TTL gate 14. While the current mirror transistor element Q5 in current mirror branch circuit 16 operates in the linear or non-saturation operating region characteristic of the emitter coupled logic, the inverting stage transistor element Q6 operates in the non-linear saturation operating region characteristic of the TTL gate transistor elements. The reference voltage level shifted output signal directly drives the first stage transistor element associated with the TTL gate and operating in the non-linear saturation region. The dividing line between components operating in the linear non-saturation operating region characteristic of the emitter coupled logic, and the components operating in the non-linear saturation operating region characteristic of the transistor transistor logic is indicated by dash line 18.
The first stage saturation region transistor element Q6 is coupled to the base of phase splitter transistor element Q9 of the TTL gate 14 through diode D1. This TTL input circuit includes Q6 collector lead resistor R6 and Q9 base resistor R16 coupled to V.sub.CC . The collector node of inverting stage saturation region transistor element Q6 is coupled through the boot strap circuit provided by boot strap transistor element Q7 and resistor R7 to the base node of transistor element Q6 and to the reference voltage level shifted collector node of current mirror transistor element Q5. The boot strap current applied through resistor R7 after the base of first stage TTL transistor element Q6 is discharged, assures that current mirror transistor element Q5 remains out of the saturation operating region and in the linear operating region.
A disadvantage of the conventional translator circuit 10 of FIG. 1 is that the current mirror circuit is a switching current mirror circuit. The current mirror transistor elements Q4 and Q5 switch between two different emitter current densities in response to switching between high and low logic levels at the collector node of ECL input transistor Q1 and switching of the emitter current from emitter follower buffer transistor element Q1A. The switching of emitter current densities by current mirror transistor Q4 is mirrored by current mirror transistor Q5. The current mirror current source transistor elements Q4 and Q5 can respond only slowly with delayed switching of the voltage level at the collector node of current mirror transistor element Q5 according to the high or low switching level at the input of ECL input transistor Q1. Because of the slow switching response of current source transistors Q4 and Q5, inherent propagation delays are introduced in the translator section 10.
Furthermore, discharge of the base of the first saturation stage transistor element Q6 takes place directly through the current mirror transistor element Q5. The switching from high to low voltage level at the collector node of current mirror transistor element Q5, and discharge of the base of transistor element Q6 operating in the saturation region, follows a delayed linear ramp function as shown for example in FIG. 1A. Overall, the same level switching node of transistor element Q5 where the reference voltage level shift occurs also drives the base of the first stage transistor element Q6 operating in the TTL saturation operating region. The result is delayed propagation during high to low switching transitions and in particular slow down in the signal propagation time tpHL during transition from high to low potential at the ECL gate input and TTL gate output.
The TTL gate 14 is provided by the conventional components including the Darlington pair of pullup transistor elements Q11 and Q12 for sourcing current from the high potential power supply rail V.sub.CC (TTL) to the output V.sub.OUT (TTL). Pulldown transistor element Q13 sinks current from the output V.sub.OUT (TTL) to the lower ground potential rail GND (TTL). Resistor R12 and diode D12 provide resistive pulldown discharge for the base of pulldown transistor element Q13. An "A.C. Miller killer" of the type described in U.S. Pat. No. 4,321,490, for active discharge of capacitive feedback Miller current at the base of pulldown transistor element Q13 is provided by active discharge transistor Q14 and associated diode network D9, D10, and D11. Accelerated switching of the output from high to low potential is provided by feedback transistor Q10 with feedback transistor base drive through resistor R10 and diode D6. Speed up diode D5 accelerates turnoff at the base of Darlington transistor Q12 during transition from high to low potential at the output V.sub.OUT (TTL). Additional bias components associated with the Darlington pullup transistor elements Qll and Q12 include resistor R11, diode D7 and diode D8.
An historic disadvantage of TTL circuits generally in comparison with ECL circuits is the operation of TTL gate transistor elements and switching transistor elements in the saturation operating region of the transistors. The saturation operating region is characterized by minority charge carrier storage in the base of the transistor element. For a P type material base in NPN transistors, electrons are the minority charge carriers. Discharge of the stored charge carriers from the base required for turn off of the TTL transistor element introduces switching delays and consequent signal propagation delay through the TTL circuit. In the TTL output buffer circuit of FIG. 1, dissipation of the charge carriers stored in saturation increases signal propagation time tpLH during transition from low to high potential at the output when the phase splitter transistor element Q9 and pulldown transistor element Q13 are turning off. Further background on TTL transistor elements and circuits follows.
Transistor-transistor logic (TTL) is widely used for bipolar transistor circuits such as the FAST.RTM. Fairchild Advanced Schottky TTL circuits. This family of integrated circuit (IC) devices is described in a Databook published by National Semiconductor Corporation in 1988 entitled "FAST.RTM. ADVANCED SCHOTTKY TTL LOGIC". The contents of this Databook are incorporated herein by reference. The FAST.RTM. devices are fabricated using the well known Isoplanar II technology which produces integrated circuit transistors with well-controlled switching speed, extremely small parasitic capacitance, and high switching frequency f.sub.T in excess of 5 GHz. These small transistors operate with currents in the range of a few milliamperes. The TTL IC devices are useful in conventional logic configurations employed in small scale integration (SSI), medium scale integration (MSI), and in large scale integration (LSI). SSI circuits are designed to provide relatively large output currents or high "fan-out" capability for driving a large number of loads and for driving capacitive loads. In MSI and LSI circuits the elementary gate circuits may communicate only with other internal gates of the IC chip. It is not necessary to provide the high drive, high "fan-out" capability of the SSI construction for such internal gates. However, output gates that communicate with off chip elements ordinarily require the high drive, high "fan-out" capability.
TTL circuits conventionally use the so called "Schottky clamped" transistor construction to reduce the transistor turn off delays that are associated with minority carrier storage in saturation. In this device a Schottky barrier diode, simply referred to herein as a Schottky diode, is connected between the transistor collector and base. When the transistor turns on, the collector potential falls below the base potential by an amount equal to the voltage drop V.sub.SD across a Schottky diode. The Schottky diode then conducts and clamps the collector-to-base potential at the forward conduction potential across the Schottky diode. This bias level is substantially below the level at which the collector will inject or flood the base with significant minority carriers and is referred to as "soft saturation". Minority charge carrier storage is substantially avoided or minimized along with the excessive transistor turn off delay that is ordinarily associated with a saturated transistor. The Schottky diode clamped transistors can be made for fast switching with very low capacitances. However, Schottky clamped TTL transistor elements have a relatively high forward conducting voltage drop and require the extra fabrication step of diode formation.
Furthermore, while the Schottky diode will prevent deep saturation in a PN junction transistor at room temperature, the Schottky diode forward voltage drop does not track the same minority carrier injecting level or maintain the soft saturation level of the transistor at all temperatures. Increased minority carrier storage is observed with increased gate propagation delay for the low-to-high output logic transition at higher temperatures. Typically, such increased delays are evident above about 100.degree. C.